Metal-metal bonding today finds many applications in the field of microelectronics or nanotechnologies. By way of example, it is used for encapsulating MEMS components, for making electrodes in photovoltaic cells and for making heat sinks in power components.
The metal bonding is also involved in the manufacture of three dimension integrated circuits (3D-IC), because it enables several semi-conductor substrates containing metal interconnections to be vertically stacked while ensuring electrical continuity between these interconnections. The assembled substrates generally have a metal/dielectric hybrid bonding surface, that is a substrate comprised of pads and/or metal lines surrounded by a dielectric material. The bonding thereby requires an alignment of the metal interconnections belonging to both substrates.
Several known metal bonding techniques enable two substrates to be assembled without introducing an intermediate compound—such as an adhesive, a wax or a low melting alloy—at the bonding interface.
By way of example, the direct (non thermo-compressive) bonding method of copper comprises contacting, generally at ambient temperature, two copper layers the surfaces of which are smooth, hydrophilic and free of contamination. In this case, the attractive forces between both copper layers (Van der Waals forces in particular) are sufficiently high to cause adhesion between both substrates. The assembly of both substrates is then subjected to a so-called stabilization post-bonding annealing to make bonding irreversible, mechanically robust and electrically conductive.
According to document [“An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization”, L. Di Cioccio et al., Journal of The Electrochemical Society, No. 158, pp. 81-86, 2011], the direct bonding can be made in the air and at ambient temperature. Thereby, the presence of copper oxide layers is observed at the bonding interface. These copper oxide layers can be detrimental to the bonding quality, despite that copper oxide is thermally instable and disappears during the stabilization annealing. The direct bonding can also be achieved under ultra-high vacuum (UHV) to avoid the formation of copper oxide layers at the surface. However, pieces of equipment enabling an ultra-high vacuum to be created and maintained are particularly expensive and slow, which limits the use of this technique.
The direct bonding method at ambient temperature and pressure is simpler to implement than other metal bonding techniques, in particular the thermo-compression assisted copper bonding method. Further, the stabilization annealing is made at low temperature (about 300° C.), which avoids to worsen the properties of the components formed in the substrates. However, the quality of the direct bonding is dependent on the surface state of the copper layers before bonding. Chemical-mechanical polishing and washing steps are thus generally accomplished to improve this surface state.
The main drawback of the direct bonding highlighted by literature is the presence of defects after annealing, not only at the bonding interface between both copper layers, but also at the interfaces between each copper layer and the substrate on which the layer has been deposited. These defects are generally in the form of voids and dislocations. In the case of a 3D-IC integration, these defects cause in particular open lines (interconnection cut-out) or extrusion and then interconnection short-circuit phenomena.
Copper oxide residues can be responsible for a part of the defects at the bonding interface. However, as discussed in the paper [“Effect of Copper-Copper Direct Bonding on Voiding in Metal Thin Films”, P. Gondcharton et al., Journal of Electronic Materials, Vol. 44, No. 11, pp. 4128-4132, 2015], the main origin of the other defects seems to be the mechanical stresses which are exerted in both contacting copper layers during the stabilization annealing. These mechanical stresses are due to the expansion coefficient difference between copper and the material of the substrates which support the copper layers (herein, silicon).
FIG. 1 shows the evolution of the in-plane biaxial stress σ of two copper layers after being bonded, as a function of the temperature T of the stabilization annealing. The positive values of the stress σ correspond to a tensile stress σ and the negative values of the stress σ correspond to a compressive stress.
The stabilization annealing corresponds to a heat cycle comprising a temperature rise (lower curve) from the ambient temperature (here 25° C.) up to a temperature of 300° C., and then a cooling (upper curve). The temperature rise consists of two successive phases P1 and P2. During the first phase P1 (25° C. to 100° C.), referred to as thermo-elastic phase, the stress σ of the copper layers substantially linearly decreases (in relative value), up to reach the compressive yield strength of copper. This phase P1 is only governed by the heat expansion difference between the substrates (silicon) and the copper layers. During the second phase P2 (100° C.-300° C.), the stress σ is maintained at the compressive yield strength. This plateau phase P2 corresponds to a plasticity regime of the copper layers, which accommodate the inner deformations by creep and void nucleation mechanisms. During this phase P2, defects are created at the interfaces with the copper layers. Finally, the third phase P3 corresponding to cooling is another thermo-elastic phase, where the stress σ linearly increases, switching from a negative value (compressive stress) to a positive value (tensile stress).